The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device having a reset circuit connected to a data bus pair.
As is well known, a semiconductor memory device generally comprises a memory cell array, a row decoder coupled to the memory cell array through word lines, an address buffer coupled to the row decoder, a sense amplifier and input/output gate coupled to the memory cell array through bit line pairs, a column decoder coupled to the sense amplifier and input/output gate, an address buffer coupled to the column decoder, input and output buffers coupled to the sense amplifier and input/output gate through a data bus pair, and the like. The data bus pair is reset before each read operation to a power source voltage or a ground voltage.
In the case where the reset voltage of the data bus pair is set to the power source voltage, the input/output gate is not turned ON until the voltage of a clock signal for opening and closing (that is, turning ON and OFF) the input/output gate exceeds a sum of a bit line potential and a threshold voltage of transistors constituting the input/output gate. But in the case where the reset voltage of the data bus pair is set to the ground voltage, the input/output gate is turned ON when the clock signal voltage exceeds the threshold voltage, and the timing with which the input/output gate is turned ON is quicker compared to the case where the reset voltage of the data bus pair is set to the power source voltage.
The output buffer outputs a read-out data by amplifying a potential difference between the two data buses constituting the data bus pair. For this reason, when it takes time for the potential difference to occur at the data bus pair, it takes that much longer for the output buffer to output the read-out data. In order to realize a memory device which operates at a high speed, it is necessary to speed up the data transfer between the bit line pair and the data bus pair.
In order to realize the high-speed data transfer between the bit line pair and the data bus pair, it is desirable to set the reset voltage of the data bus pair to the ground voltage. However, when the reset voltage is set to the ground voltage, the input/output gate is also turned ON when a noise is mixed in the clock signal and the clock signal voltage exceeds the threshold voltage. The turning ON of the input/output gate due to the noise may only occur for an instant, but there is a problem in that the charges on the bit line pair may leak thereby. A ground line for a clock generating circuit which generates the clock signal for the input/output gate is different from a ground line of a reset circuit for resetting the data bus pair, and the noise (or voltage increase) in the clock signal is inevitable since the noise is generated when a relatively large current flows to the ground line of the clock generating circuit.